The present invention relates to the fabrication of integrated circuits. More particularly, embodiments of the invention include methods and apparatuses for improving the quality of films deposited in a substrate processing chamber by reducing the number of particles formed on the backside of a wafer.
The geometry of semiconductor devices has decreased dramatically in size since such devices were first introduced several decades ago. Integrated circuits have generally followed the two year/half-size rule (often called xe2x80x9cMoore""s Lawxe2x80x9d) which states that the number of devices fitting on a chip will double every two years. Today""s wafer fabrication plants are routinely producing integrated circuits having 0.5 and even 0.35 micron feature sizes, and tomorrow""s plants soon will be producing devices having even smaller geometries.
During chemical vapor deposition (CVD) of material layers making up these semiconductor devices, improved control over criteria such as particle generation and contamination is necessary to ensure that deposited layers meet the stringent specifications of manufacturers. In order to meet processing demands created by such small scale geometry devices, new technology for substrate processing equipment is constantly being developed.
For example, as device sizes become smaller and integration density increases, issues not previously considered important are emerging as areas of concern. One such issue is backside wafer contamination.
Particle contamination on the backside of wafers has become a serious issue in advanced microelectronics manufacturing for several reasons. One reason is that particles on the backside of the wafer can cause cross contamination and electrical contact failures in interconnect structures.
A second reason for the importance of wafer backside particle contamination is change in wafer planarity associated with such contamination. Specifically, particles present on the backside of the wafer can impact control over the critical dimension (CD) in lithographic processes by causing wafer warpage. The depth of focus in sub-half micron lithography is approximately xc2x10.5 xcexcm, and factors such as field image curvature, circuit topography, wafer flatness and auto-focus errors reduce the usable focus margin. Therefore, ensuring the planarity of wafers during the lithographic process becomes more critical in obtaining tight CD control.
Anti reflective coatings (ARC) formed by plasma-enhanced chemical vapor deposition (PECVD) have been widely used to control CD during photolithography processing steps by suppressing over 99% of light reflected from a substrate. In general however, wafers that have received an ARC film must generally be subjected to additional processing steps in order to remove particles on the wafer backside before the wafer is exposed to lithography steps.
One such additional processing step is wafer backside scrubbing, but this technique cannot completely remove defects on the backside of wafers when such defects are the result of chemical reaction involving deposited material. Some residual defects still remain on wafers even after the back side scrubbing due to inherent limitations in wet chemical etching.
Therefore, there is a need in the art for methods and apparatuses which reduce particle contamination on the wafer backside during CVD processes.
One embodiment of the present invention provides methods and apparatuses of reducing the number of particles and other contaminants formed on the backside of wafers during semiconductor processing. Specifically, a number of techniques may be utilized, alone or in combination, to reduce the level of backside particulate contamination.
First, following a periodic chamber cleaning step, an oxide seasoning reaction is performed to coat interior chamber surfaces and the wafer heater with an oxide coating. Second, wafers entering the CVD chamber are preheated before being placed into direct physical contact with the wafer heater structure, thereby reducing thermal stress imposed on the wafer. Third, the flow time of deposition process gases during pre-deposition stabilization steps are kept to a minimum, thereby reducing decomposition of deposition process gases and contamination between the heater surface and the wafer back side. Fourth, a minimum contact wafer heater structure is employed to support and heat the wafer during processing. This heater structure contacts as small an area of the back side of the wafer as possible, and also restricts the flow of process gases against the wafer back side. Each of these techniques is discussed in detail below.
A wafer heater apparatus in accordance with one embodiment of the present invention comprises a pedestal including a heated circular top surface, and a plurality of projections extending upward from the circular top surface. An elevated rim is positioned around a circumference of the top surface.
An embodiment of a method for depositing material on a semiconductor wafer comprises providing a substantially circular semiconductor wafer having a front side and a back side, and providing a wafer heater at a first temperature, the wafer heater including a top surface featuring a plurality of projections and an elevated circumferential rim. The back side of the semiconductor wafer is placed into contact with the heater, such that an edge of the wafer is supported by the rim. The rim interferes with the flow of process gases from the front side of the wafer to the back side of the wafer.
A further understanding of the objects and advantages of the present invention can be made by way of reference to the ensuing detailed description taken in conjunction with the accompanying drawings.